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回复 10# mordorwww
In a GIC that does not support interrupt grouping:
• the GICD_CTLR.Enable bit controls the forwarding of interrupts from the Distributor to the CPU interfaces
• the GICC_CTLR.Enable bit controls the signaling of interrupts by the CPU interface to the connected
processor.
For the Distributor:
• When GICD_CTLR.Enable is set to 1, the Distributor forwards the highest priority pending interrupt for each
CPU interface, subject to the prioritization rules.
• When GICD_CTLR.Enable is set to 0:
— the Distributor does not forward pending interrupts to the CPU interfaces
— it is IMPLEMENTATION DEFINED whether an edge-triggered interrupt signal sets the interrupt to the
pending state.
— reads of GICC_IAR, GICC_AIAR, GICC_HPPIR, or GICC_AHPPIR return a spurious interrupt ID
— software can read or write the Distributor registers
— it is IMPLEMENTATION DEFINED whether SGIs can be set pending using GICD_SGIR.
看起来如果屏蔽某个edge interrupt的话,来中断的话,实现相关可能不会设置pending状态,那么中断就丢失了。
level interrupt没有这个问题,不管屏蔽没有,都会设置pending
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