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机器自检不通过, 连OBP也进不去(附自检信息) [复制链接]

rebellion

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发表于 2005-03-08 01:43 |只看该作者 |倒序浏览
有人私自改了nvalias, 现在连OBP也进不去了, 请各位大侠帮忙看看, 如何修复, 谢谢!!

Hardware Power ON

@(#) Ultra Enterprise 3.2 Version 24 created 1999/12/23 17:31
CPU = 0000.0000.0000.0000
Probing keyboard Done

0,0>;
0,0>;@(#) POST 3.9.24 1999/12/23 17:35
0,1>;
0,0>;
    SelfTest Initializing (Diag Level 10, ENV 00004001) IMPL 0011 MASK 11
0,1>;@(#) POST 3.9.24 1999/12/23 17:35
0,0>;Board 0 CPU FPROM Test
0,1>;
    SelfTest Initializing (Diag Level 10, ENV 00000000) IMPL 0011 MASK 11
0,0>;Board 0 Basic CPU Test
0,0>;    Set CPU UPA Config and Init SDB Data
0,0>;    SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0
0,0>;Board 0 MMU Enable Test
0,0>;    DMMU Init
0,0>;    IMMU Init
0,0>;    Mapping Selftest Enabling MMUs
0,0>;Board 0 Ecache Test
0,0>;    Ecache Probe
0,0>;    Ecache Tags
0,1>;Board 0 CPU FPROM Test
0,1>;Board 0 Basic CPU Test
0,1>;    Set CPU UPA Config and Init SDB Data
0,1>;    SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0
0,1>;Board 0 MMU Enable Test
0,1>;    DMMU Init
0,1>;    IMMU Init
0,1>;    Mapping Selftest Enabling MMUs
0,1>;Board 0 Ecache Test
0,1>;    Ecache Probe
0,1>;    Ecache Tags
0,0>;    Ecache Quick Verify
0,1>;    Ecache Quick Verify
0,0>;    Ecache Init
0,1>;    Ecache Init
0,0>;    Ecache RAM
0,0>;    Ecache Address Line
0,0>;    Configure Ecache Limit
0,0>;Ecache Size = 00100000,  Limited to 00100000
0,0>;Board 0 FPU Functional Test
0,0>;    FPU Enable
0,0>;Board 0 Board Master Select Test
0,0>;    Selecting a Board Master
0,0>;Board 0 FireHose Devices Test
0,1>;    Ecache RAM
0,1>;    Ecache Address Line
0,1>;    Configure Ecache Limit
0,1>;Ecache Size = 00100000,  Limited to 00100000
0,1>;Board 0 FPU Functional Test
0,1>;    FPU Enable
0,1>;Board 0 Board Master Select Test
0,1>;    Selecting a Board Master
0,0>;Board 0 Address Controller Test
0,0>;    AC Initialization
0,0>;    AC DTAG Init
0,0>;Board 0 Dual Tags Test
0,0>;    AC DTAG Init
0,0>;Board 0 FireHose Controller Test
0,0>;    FHC Initialization
0,0>;Board 0 JTAG Test
0,0>;    Verify System Board Scan Ring
0,0>;Board 0 Centerplane Test
0,0>;    Centerplane Join
0,0>;Setting JTAG Master
0,0>;Clear JTAG Master
0,0>;Board 0 Setup Cache Size Test
0,0>;    Setting Up Cache Size
0,0>;Board 0 System Master Select Test
0,0>;    Setting System Master
0,0>OST Master Selected (JTAG,CENTRAL)
0,0>;Board 16 Clock Board Test
0,0>;    Clock Board Initialization
0,0>;    Clock Board Temperature Check
0,0>;Board 16 Clock Board Serial Ports Test
0,0>;Board 16 NVRAM Devices Test
0,0>;    M48T59 (TOD) Init
0,0>;Board 0 System Board Probe  Test
0,0>;    Probing all CPU/Memory BDA
0,0>;    Probing System Boards
0,0>;    Probing CPU Module JTAG Rings
0,0>;Setting System Clock Frequency
0,0>;    CPU Module mid 0 Checked in OK (speed code = 4)
0,0>;    CPU mid 1 Version=00170011.11000507
0,0>;    CPU Module mid 1 Checked in OK (speed code = 4)
0,0>;    CPU mid 4 Version=00170011.11000507
0,0>;    CPU Module mid 4 Checked in OK (speed code = 4)
0,0>;    CPU mid 5 Version=00170011.11000507
0,0>;    CPU Module mid 5 Checked in OK (speed code = 4)
0,0>;    CPU mid 8 Version=00170011.11000507
0,0>;    CPU Module mid 8 Checked in OK (speed code = 4)
0,0>;    CPU mid 9 Version=00170011.11000507
0,0>;    CPU Module mid 9 Checked in OK (speed code = 4)
0,0>; ******** Clock Reset - retesting
0,0>;System Frequency (MHz),fcpu=248, fmod=124, fsys=82, fgen=496
0,0>;
0,0>;@(#) POST 3.9.24 1999/12/23 17:35
0,1>;
0,0>;
    SelfTest Initializing (Diag Level 40, ENV 00004081) IMPL 0011 MASK 11
0,1>;@(#) POST 3.9.24 1999/12/23 17:35
0,0>;Board 0 CPU FPROM Test
0,1>;
    SelfTest Initializing (Diag Level 40, ENV 00004081) IMPL 0011 MASK 11
0,0>;    CPU/Memory Board FPROM Checksum Test
0,1>;Board 0 CPU FPROM Test
0,1>;    CPU/Memory Board FPROM Checksum Test
0,0>;Board 0 Basic CPU Test
0,0>;    FPU Registers and Data Path Test
0,0>;    Instruction Cache Tag RAM Test
0,1>;Board 0 Basic CPU Test
0,1>;    FPU Registers and Data Path Test
0,1>;    Instruction Cache Tag RAM Test
0,0>;    Instruction Cache Instruction RAM Test
0,1>;    Instruction Cache Instruction RAM Test
0,0>;    Instruction Cache Next Field RAM Test
0,1>;    Instruction Cache Next Field RAM Test
0,0>;    Instruction Cache Pre-decode RAM Test
0,1>;    Instruction Cache Pre-decode RAM Test
0,0>;    Data Cache RAM Test
0,1>;    Data Cache RAM Test
0,0>;    Data Cache Tags Test
0,1>;    Data Cache Tags Test
0,0>;    DMMU Registers Access Test
0,0>;    DMMU TLB DATA RAM Access Test
0,0>;    DMMU TLB TAGS Access Test
0,0>;    IMMU Registers Access Test
0,0>;    IMMU TLB DATA RAM Access Test
0,0>;    IMMU TLB TAGS Access Test
0,1>;    DMMU Registers Access Test
0,0>;    Set CPU UPA Config and Init SDB Data
0,0>;    SRAM Mode = 22, Clock Mode = 3:1, PCON = 6b3, MCAP = 0
0,1>;    DMMU TLB DATA RAM Access Test
0,0>;Board 0 MMU Enable Test
0,0>;    DMMU Init
0,0>;    IMMU Init
0,0>;    Mapping Selftest Enabling MMUs
0,1>;    DMMU TLB TAGS Access Test
0,0>;Board 0 Ecache Test
0,0>;    Ecache Probe
0,0>;    Ecache Tags
0,1>;    IMMU Registers Access Test
0,1>;    IMMU TLB DATA RAM Access Test
0,1>;    IMMU TLB TAGS Access Test
0,1>;    Set CPU UPA Config and Init SDB Data
0,1>;    SRAM Mode = 22, Clock Mode = 3:1, PCON = 6b3, MCAP = 0
0,1>;Board 0 MMU Enable Test
0,1>;    DMMU Init
0,1>;    IMMU Init
0,1>;    Mapping Selftest Enabling MMUs
0,1>;Board 0 Ecache Test
0,1>;    Ecache Probe
0,1>;    Ecache Tags
0,0>;    Ecache Quick Verify
0,0>;    Ecache Init
0,1>;    Ecache Quick Verify
0,1>;    Ecache Init
0,0>;    Ecache RAM
0,0>;    Ecache 6N RAM Pattern Test
0,1>;    Ecache RAM
0,0>;    Ecache Address Line
0,0>;    Configure Ecache Limit
0,0>;Ecache Size = 00100000,  Limited to 00100000
0,1>;    Ecache 6N RAM Pattern Test
0,0>;Board 0 FPU Functional Test
0,0>;    FPU Enable
0,0>;Board 0 Board Master Select Test
0,0>;    Selecting a Board Master
0,0>;Board 0 FireHose Devices Test
0,0>;    PROM Datapath Test
0,0>;    FHC CPU SRAM Test
0,1>;    Ecache Address Line
0,1>;    Configure Ecache Limit
0,1>;Ecache Size = 00100000,  Limited to 00100000
0,1>;Board 0 FPU Functional Test
0,1>;    FPU Enable
0,1>;Board 0 Board Master Select Test
0,1>;    Selecting a Board Master
0,0>;Board 0 Address Controller Test
0,0>;    AC Registers Test
0,0>;    AC Initialization
0,0>;    Memory Registers  Test
0,0>;    Memory Registers Initialization Test
0,0>;    AC DTAG Init
0,0>;Board 0 Dual Tags Test
0,0>;    AC DTAG Test
0,0>;    AC DTAG Init
0,0>;Board 0 FireHose Controller Test
0,0>;    FHC Initialization
0,0>;Board 0 JTAG Test
0,0>;    Verify System Board Scan Ring
0,0>;Board 0 Centerplane Test
0,0>;    Centerplane and Arbiter Check Test
0,0>;Setting JTAG Master
0,0>;Clear JTAG Master
0,0>;    Centerplane Join
0,0>;Setting JTAG Master
0,0>;Clear JTAG Master
0,0>;Board 0 Setup Cache Size Test
0,0>;    Setting Up Cache Size
0,0>;Board 0 System Master Select Test
0,0>;    Setting System Master
0,0>OST Master Selected (JTAG,CENTRAL)
0,0>;Board 16 Clock Board Test
0,0>;    Clock Board Registers Test
0,0>;    Clock Board Initialization
0,0>;    Clock Board Temperature Check
0,0>;Board 16 Clock Board Serial Ports Test
0,0>;    85C30 Register Test
0,0>;    85C30 Serial Ports Test
0,0>;    Keyboard Loopback
0,0>;    Mouse Loopback
0,0>;    Serial Port B Loopback
0,0>;    Remote Serial Port A Loopback
0,0>;    Remote Serial Port B Loopback
0,0>;Board 16 NVRAM Devices Test
0,0>;    M48T59 (TOD) Init
0,0>;    M48T59 (TOD) Functional Part 1 Test
0,0>;    NVRAM(Non-Destructive) Test
0,0>;Board 0 System Board Probe  Test
0,0>;    Probing all CPU/Memory BDA
0,0>;    Probing System Boards
0,0>;    Probing CPU Module JTAG Rings
0,0>;Setting System Clock Frequency
0,0>;    CPU Module mid 0 Checked in OK (speed code = 4)
0,0>;    CPU mid 1 Version=00170011.11000507
0,0>;    CPU Module mid 1 Checked in OK (speed code = 4)
0,0>;    CPU mid 4 Version=00170011.11000507
0,0>;    CPU Module mid 4 Checked in OK (speed code = 4)
0,0>;    CPU mid 5 Version=00170011.11000507
0,0>;    CPU Module mid 5 Checked in OK (speed code = 4)
0,0>;    CPU mid 8 Version=00170011.11000507
0,0>;    CPU Module mid 8 Checked in OK (speed code = 4)
0,0>;    CPU mid 9 Version=00170011.11000507
0,0>;    CPU Module mid 9 Checked in OK (speed code = 4)
0,0>;System Frequency (MHz),fcpu=248, fmod=124, fsys=82, fgen=496
0,0>;TESTING BOARD 1
0,0>;Board 1 JTAG Test
0,0>;    Verify System Board Scan Ring
0,0>;Board 1 Centerplane Test
0,0>;    Centerplane Check
0,0>;Board 1 Address Controller Test
0,0>;    AC Registers Test
0,0>;    AC Initialization
0,0>;Setting Freq to 25MHZ
0,0>;    Memory Registers  Test
0,0>;    Memory Registers Initialization Test
0,0>;    AC DTAG Init
0,0>;Board 1 FireHose Controller Test
0,0>;    FHC Initialization
0,0>;Board 1 NVRAM Devices Test
0,0>;    M48T59 (TOD) Init
0,0>;    M48T59 (TOD) Functional Part 1 Test
0,0>;    NVRAM(Non-Destructive) Test
0,0>;TESTING BOARD 6
0,0>;Board 6 JTAG Test
0,0>;    Verify System Board Scan Ring
0,0>;Board 6 Centerplane Test
0,0>;    Centerplane Check
0,0>;Board 6 Address Controller Test
0,0>;    AC Registers Test
0,0>;    AC Initialization
0,0>;Setting Freq to 25MHZ
0,0>;    Memory Registers  Test
0,0>;    Memory Registers Initialization Test
0,0>;    AC DTAG Init
0,0>;Board 6 FireHose Controller Test
0,0>;    FHC Initialization
0,0>;Board 6 NVRAM Devices Test
0,0>;    M48T59 (TOD) Init
0,0>;    M48T59 (TOD) Functional Part 1 Test
0,0>;    NVRAM(Non-Destructive) Test
0,0>;Re-mapping to Local Device Space
0,0>;Begin Central Space Serial Port access
0,0>;Enable AC Control Parity
0,0>;Hotplug Trigger Test
0,0>;Init Counters for Hotplug
0,0>;Board 0 Cross Calls Test
0,0>;    Cross Calls Test
0,0>;Displaying PROM Versions
0,0>;Slot 0 CPU/Memory   OBP   3.2.24 1999/12/23 17:31  POST  3.9.24 1999/12/23 17:35
0,0>;Slot 1 IO Type 1    FCODE 1.8.24 1999/12/23 17:29  iPOST 3.4.24 1999/12/23 17:34
0,0>;Slot 2 CPU/Memory   OBP   3.2.24 1999/12/23 17:31  POST  3.9.24 1999/12/23 17:35
0,0>;Slot 4 CPU/Memory   OBP   3.2.24 1999/12/23 17:31  POST  3.9.24 1999/12/23 17:35
0,0>;Slot 6 IO Type 1    FCODE 1.8.24 1999/12/23 17:29  iPOST 3.4.24 1999/12/23 17:34
0,0>;Board 0 Environmental Probe Test
0,0>;    Environmental Probe
0,0>;Checking Power Supply Configuration
0,0>ower is more than adequate, load 5 ps 4
0,0>;Reconfig memory due to POR or CLOCK RESET
0,0>;Reconfig memory due to DIAG_LEVEL
0,0>;Board 0 Probing Memory SIMMS Test
0,0>;    Probe SIMMID
0,0>;    Populated Memory Bank Status
0,0>;            bd #    Size    Address Way     Status
0,0>;            0       256                     Normal
0,0>;            0       256                     Normal
0,0>;            2       256                     Normal
0,0>;            2       256                     Normal
0,0>;            4       256                     Normal
0,0>;            4       256                     Normal
0,0>;Board 0 Memory Configuration Test
0,0>;    Memory Interleaving
0,0>;    Total banks with 8MB SIMMs = 0
0,0>;    Total banks with 32MB SIMMs = 6
0,0>;    Total banks with 128MB SIMMs = 0
0,0>;    Total banks with 256MB SIMMs = 0
0,0>;    Overall memory default speed = 60ns
0,0>;Do OPTIMAL INTLV
0,0>;    Board 0 AC rev 5 RCTIME = 0 (Tras 71)
0,0>;    Board 2 AC rev 5 RCTIME = 0 (Tras 71)
0,0>;    Board 4 AC rev 5 RCTIME = 0 (Tras 71)
0,0>;    Board 0 AC rev 5 RCTIME = 0 (Tras 71)
0,0>;    Board 2 AC rev 5 RCTIME = 0 (Tras 71)
0,0>;    Board 4 AC rev 5 RCTIME = 0 (Tras 71)
0,0>;    Memory Refresh Enable
0,0>;Board 0 SIMMs Test
0,0>;    MP Memory SIMM Clear Test
0,0>;    Memory Size is 1536Mbytes
0,0>;      CPU MID 1 clearing 00000000.00004000 to 00000000.10000000
0,0>;      CPU MID 4 clearing 00000000.10000000 to 00000000.20000000
0,0>;      CPU MID 5 clearing 00000000.20000000 to 00000000.30000000
0,0>;      CPU MID 8 clearing 00000000.30000000 to 00000000.40000000
0,0>;      CPU MID 9 clearing 00000000.40000000 to 00000000.50000000
0,0>;      CPU MID 0 clearing 00000000.50000000 to 00000000.60000000
0,0>;      CPU MID 0 clearing 00000000.00000000 to 00000000.00004000
0,0>;    Memory Walking Rows and Columns Test
0,0>;    MP Memory SIMM (6N RAM Patterns) Test
0,0>;    Memory Size is 1536Mbytes
0,0>;      CPU MID 1 testing 00000000.00000000 to 00000000.10000000
0,0>;      CPU MID 4 testing 00000000.10000000 to 00000000.20000000
0,0>;      CPU MID 5 testing 00000000.20000000 to 00000000.30000000
0,0>;      CPU MID 8 testing 00000000.30000000 to 00000000.40000000
0,0>;      CPU MID 9 testing 00000000.40000000 to 00000000.50000000
0,0>;      CPU MID 0 testing 00000000.50000000 to 00000000.60000000
0,0>;    MP Memory SIMM (moving inverse) Test
0,0>;    Memory Size is 1536Mbytes
0,0>;      CPU MID 1 testing 00000000.00000000 to 00000000.10000000
0,0>;      CPU MID 4 testing 00000000.10000000 to 00000000.20000000
0,0>;      CPU MID 5 testing 00000000.20000000 to 00000000.30000000
0,0>;      CPU MID 8 testing 00000000.30000000 to 00000000.40000000
0,0>;      CPU MID 9 testing 00000000.40000000 to 00000000.50000000
0,0>;      CPU MID 0 testing 00000000.50000000 to 00000000.60000000
0,0>;Slave CPU Functional Tests
0,0>;     Slave CPU MID 1 started
0,1>;Board 0 Functional CPU 1 Test
0,1>;    Dcache Init
0,1>;    Dcache Enable Test
0,1>;    Dcache Functionality Test
0,1>;    Ecache Stress Test
0,1>;    Ecache Functional Test
0,1>;    CPU Dispatch (Multi-Scalar) Test
0,1>;    SPARC Atomic Instructions Test
0,1>;    SPARC Prefetch Instructions Test
0,1>;    CPU Softint Registers and Interrupts Test
0,1>;    Uni-Processor Cache Coherence Test
0,1>;    Branch Memory Test
0,1>;    SDB ECC CE Test
0,1>;    SDB ECC Uncorrectable Test
0,1>;    FPU Instruction Test
0,0>;     Slave CPU MID 4 started
2,0>;Board 2 Functional CPU 0 Test
2,0>;    Dcache Init
2,0>;    Dcache Enable Test
2,0>;    Dcache Functionality Test
2,0>;    Ecache Stress Test
2,0>;    Ecache Functional Test
2,0>;    CPU Dispatch (Multi-Scalar) Test
2,0>;    SPARC Atomic Instructions Test
2,0>;    SPARC Prefetch Instructions Test
2,0>;    CPU Softint Registers and Interrupts Test
2,0>;    Uni-Processor Cache Coherence Test
2,0>;    Branch Memory Test
2,0>;    SDB ECC CE Test
2,0>;    SDB ECC Uncorrectable Test
2,0>;    FPU Instruction Test
0,0>;     Slave CPU MID 5 started
2,1>;Board 2 Functional CPU 1 Test
2,1>;    Dcache Init
2,1>;    Dcache Enable Test
2,1>;    Dcache Functionality Test
2,1>;    Ecache Stress Test
2,1>;    Ecache Functional Test
2,1>;    CPU Dispatch (Multi-Scalar) Test
2,1>;    SPARC Atomic Instructions Test
2,1>;    SPARC Prefetch Instructions Test
2,1>;    CPU Softint Registers and Interrupts Test
2,1>;    Uni-Processor Cache Coherence Test
2,1>;    Branch Memory Test
2,1>;    SDB ECC CE Test
2,1>;    SDB ECC Uncorrectable Test
2,1>;    FPU Instruction Test
0,0>;     Slave CPU MID 8 started
4,0>;Board 4 Functional CPU 0 Test
4,0>;    Dcache Init
4,0>;    Dcache Enable Test
4,0>;    Dcache Functionality Test
4,0>;    Ecache Stress Test
4,0>;    Ecache Functional Test
4,0>;    CPU Dispatch (Multi-Scalar) Test
4,0>;    SPARC Atomic Instructions Test
4,0>;    SPARC Prefetch Instructions Test
4,0>;    CPU Softint Registers and Interrupts Test
4,0>;    Uni-Processor Cache Coherence Test
4,0>;    Branch Memory Test
4,0>;    SDB ECC CE Test
4,0>;    SDB ECC Uncorrectable Test
4,0>;    FPU Instruction Test
0,0>;     Slave CPU MID 9 started
4,1>;Board 4 Functional CPU 1 Test
4,1>;    Dcache Init
4,1>;    Dcache Enable Test
4,1>;    Dcache Functionality Test
4,1>;    Ecache Stress Test
4,1>;    Ecache Functional Test
4,1>;    CPU Dispatch (Multi-Scalar) Test
4,1>;    SPARC Atomic Instructions Test
4,1>;    SPARC Prefetch Instructions Test
4,1>;    CPU Softint Registers and Interrupts Test
4,1>;    Uni-Processor Cache Coherence Test
4,1>;    Branch Memory Test
4,1>;    SDB ECC CE Test
4,1>;    SDB ECC Uncorrectable Test
4,1>;    FPU Instruction Test
0,0>;Board 0 Functional CPU 0 Test
0,0>;    Dcache Init
0,0>;    Dcache Enable Test
0,0>;    Dcache Functionality Test
0,0>;    Ecache Stress Test
0,0>;    Ecache Functional Test
0,0>;    CPU Dispatch (Multi-Scalar) Test
0,0>;    SPARC Atomic Instructions Test
0,0>;    SPARC Prefetch Instructions Test
0,0>;    CPU Softint Registers and Interrupts Test
0,0>;    Uni-Processor Cache Coherence Test
0,0>;    Branch Memory Test
0,0>;    SDB ECC CE Test
0,0>;    SDB ECC Uncorrectable Test
0,0>;    FPU Instruction Test
0,0>;TESTING IO BOARD 1
0,0>;Board 1 I/O FPROM Test
0,0>;    I/O Board EPROM checksum Test
0,0>;@(#) iPOST 3.4.24 1999/12/23 17:34
0,0>; TESTING IO BOARD 1 ASICs
0,0>; TESTING SysIO Port 0
0,0>;Board 1 SysIO Registers Test
0,0>;    SysIO Register Initialization
0,0>;    IOMMU Registers and RAM Test
0,0>;    Streaming Buffer Registers and RAM Test
0,0>;    SBus Control and Config Registers Test
0,0>;    SysIO RAM Initialization
0,0>;Board 1 SysIO Functional Test
0,0>;    Clear Interrupt Map and State Registers
0,0>;    SysIO Interrupts  Test
0,0>;    SysIO Timers/Counters Test
0,0>;    IOMMU Virtual Address TLB Tag Compare Test
0,0>;    Streaming Buffer Flush Test
0,0>;    DMA Merge Buffer Test
0,0>;    SYSIO ECC Correctable Test
0,0>;    SYSIO ECC UnCorrectable Test
0,0>;    SysIO Sbus Probe Test
0,0>;    Sbus Card Installed, slot #1, addr 000001c5.10000000
0,0>;    Sbus Card Installed, slot #2, addr 000001c5.20000000
0,0>;    SysIO Register Initialization Test
0,0>;    SysIO RAM Initialization Test
0,0>;    Clear Interrupt Map and State Registers Test
0,0>;Board 1 OnBoard IO Chipset (SOC) Test
0,0>;    SOC SRAM Test
0,0>;    SOC Registers Test
0,0>;    SOC Interrupt Test
0,0>;    Clear Interrupt Map and State Registers Test
0,0>; TESTING SysIO Port 1
0,0>;Board 1 SysIO Registers Test
0,0>;    SysIO Register Initialization
0,0>;    IOMMU Registers and RAM Test
0,0>;    Streaming Buffer Registers and RAM Test
0,0>;    SBus Control and Config Registers Test
0,0>;    SysIO RAM Initialization
0,0>;Board 1 SysIO Functional Test
0,0>;    Clear Interrupt Map and State Registers
0,0>;    SysIO Interrupts  Test
0,0>;    SysIO Timers/Counters Test
0,0>;    IOMMU Virtual Address TLB Tag Compare Test
0,0>;    Streaming Buffer Flush Test
0,0>;    DMA Merge Buffer Test
0,0>;    SYSIO ECC Correctable Test
0,0>;    SYSIO ECC UnCorrectable Test
0,0>;    SysIO Sbus Probe Test
0,0>;    Sbus Card Installed, slot #0, addr 000001c7.00000000
0,0>;    SysIO Register Initialization Test
0,0>;    SysIO RAM Initialization Test
0,0>;    Clear Interrupt Map and State Registers Test
0,0>;Board 1 OnBoard IO Chipset (FEPS) Test
0,0>;    FAS366 Registers Test
0,0>;    ESP FAS366 DVMA burst mode read/write Test
0,0>;    FAS366 FIFO TO DMA Test
0,0>;    DMA TO FAS366 FIFO Test
0,0>;    FEPS (Ethernet) Registers Test
0,0>;    FEPS Ethernet(BM, DP83840, Twister) Internal Loopbacks Test
0,0>;    SysIO Register Initialization Test
0,0>;    SysIO RAM Initialization Test
0,0>;    Clear Interrupt Map and State Registers Test
0,0>;IO BOARD 1 TESTED
0,0>;TESTING IO BOARD 6
0,0>;Board 6 I/O FPROM Test
0,0>;    I/O Board EPROM checksum Test
0,0>;@(#) iPOST 3.4.24 1999/12/23 17:34
0,0>; TESTING IO BOARD 6 ASICs
0,0>; TESTING SysIO Port 0
0,0>;Board 6 SysIO Registers Test
0,0>;    SysIO Register Initialization
0,0>;    IOMMU Registers and RAM Test
0,0>;    Streaming Buffer Registers and RAM Test
0,0>;    SBus Control and Config Registers Test
0,0>;    SysIO RAM Initialization
0,0>;Board 6 SysIO Functional Test
0,0>;    Clear Interrupt Map and State Registers
0,0>;    SysIO Interrupts  Test
0,0>;    SysIO Timers/Counters Test
0,0>;    IOMMU Virtual Address TLB Tag Compare Test
0,0>;    Streaming Buffer Flush Test
0,0>;    DMA Merge Buffer Test
0,0>;    SYSIO ECC Correctable Test
0,0>;    SYSIO ECC UnCorrectable Test
0,0>;    SysIO Sbus Probe Test
0,0>;    SBus Card not Installed, slot 1 addr 000001d9.10000000
0,0>;    Sbus Card Installed, slot #2, addr 000001d9.20000000
0,0>;    SysIO Register Initialization Test
0,0>;    SysIO RAM Initialization Test
0,0>;    Clear Interrupt Map and State Registers Test
0,0>;Board 6 OnBoard IO Chipset (SOC) Test
0,0>;    SOC SRAM Test
0,0>;    SOC Registers Test
0,0>;    SOC Interrupt Test
0,0>;    Clear Interrupt Map and State Registers Test
0,0>; TESTING SysIO Port 1
0,0>;Board 6 SysIO Registers Test
0,0>;    SysIO Register Initialization
0,0>;    IOMMU Registers and RAM Test
0,0>;    Streaming Buffer Registers and RAM Test
0,0>;    SBus Control and Config Registers Test
0,0>;    SysIO RAM Initialization
0,0>;Board 6 SysIO Functional Test
0,0>;    Clear Interrupt Map and State Registers
0,0>;    SysIO Interrupts  Test
0,0>;    SysIO Timers/Counters Test
0,0>;    IOMMU Virtual Address TLB Tag Compare Test
0,0>;    Streaming Buffer Flush Test
0,0>;    DMA Merge Buffer Test
0,0>;    SYSIO ECC Correctable Test
0,0>;    SYSIO ECC UnCorrectable Test
0,0>;    SysIO Sbus Probe Test
0,0>;    SBus Card not Installed, slot 0 addr 000001db.00000000
0,0>;    SysIO Register Initialization Test
0,0>;    SysIO RAM Initialization Test
0,0>;    Clear Interrupt Map and State Registers Test
0,0>;Board 6 OnBoard IO Chipset (FEPS) Test
0,0>;    FAS366 Registers Test
0,0>;    ESP FAS366 DVMA burst mode read/write Test
0,0>;    FAS366 FIFO TO DMA Test
0,0>;    DMA TO FAS366 FIFO Test
0,0>;    FEPS (Ethernet) Registers Test
0,0>;    FEPS Ethernet(BM, DP83840, Twister) Internal Loopbacks Test
0,0>;    SysIO Register Initialization Test
0,0>;    SysIO RAM Initialization Test
0,0>;    Clear Interrupt Map and State Registers Test
0,0>;IO BOARD 6 TESTED
0,0>;SYSTEM LEVEL TESTING
0,0>;Board 0 Cache Coherency Test
0,0>;    Multi-Processor Cache Coherence Test
0,0>;    Testing CPU MID 1
0,0>;    Testing CPU MID 4
0,0>;    Testing CPU MID 5
0,0>;    Testing CPU MID 8
0,0>;    Testing CPU MID 9
0,0>robing for Disk System boards
0,0>;Board 0 System Interrupts Test
0,0>;    System Interrupts Test
0,0>;Checking Power Supply Configuration
0,0>ower is more than adequate, load 5 ps 4
0,0>;    Check Board Present Test
0,0>;    Board Present Interrupt Test
0,0>;
0,0>;    System Board Status
0,0>;-----------------------------------------------------------------
0,0>; Slot   Board Status     Board Type      Failures
0,0>;-----------------------------------------------------------------
0,0>;  0  | Normal         | CPU/Memory  |
0,0>;  1  | Normal         | IO Type 1   |
0,0>;  2  | Normal         | CPU/Memory  |
0,0>;  3  | Normal         | Disk Board  |
0,0>;  4  | Normal         | CPU/Memory  |
0,0>;  5  | Normal         | Disk Board  |
0,0>;  6  | Normal         | IO Type 1   |
0,0>;  7  | Normal         | Disk Board  |
0,0>; 16  | Normal         | Clock Board |
0,0>;-----------------------------------------------------------------
0,0>;
0,0>;    CPU Module Status
0,0>;-----------------------------------------------------------------
0,0>; MID  OK  Cache  Speed   Version
0,0>;-----------------------------------------------------------------
0,0>;  0 | y | 1024  |  248  | 00170011.11000507
0,0>;  1 | y | 1024  |  248  | 00170011.11000507
0,0>;  4 | y | 1024  |  248  | 00170011.11000507
0,0>;  5 | y | 1024  |  248  | 00170011.11000507
0,0>;  8 | y | 1024  |  248  | 00170011.11000507
0,0>;  9 | y | 1024  |  248  | 00170011.11000507
0,0>;-----------------------------------------------------------------
0,0>;System Frequency (MHz),fcpu=248, fmod=124, fsys=82, fgen=496
0,0>;    Populated Memory Bank Status
0,0>;            bd #    Size    Address Way     Status
0,0>;            0       256     0       4       Normal
0,0>;            0       256     3       4       Normal
0,0>;            2       256     1       4       Normal
0,0>;            2       256     0       2       Normal
0,0>;            4       256     2       4       Normal
0,0>;            4       256     1       2       Normal
0,0>;
0,0>;    Disk Board Status
0,0>;-----------------------------------------------------------------
0,0>;Slot        Sckt0   Sckt1
0,0>;-----------------------------------------------------------------
0,0>; 3          Disk10  Disk11
0,0>;
0,0>; 5          Disk12  Disk13
0,0>;
0,0>; 7          Disk14  Disk15
0,0>;
0,0>;
0,0>;
        POST COMPLETE
0,0>;Entering OBP

Switching to high addresses
Setting up TLBs Done
MMU ON
PC = 0000.01ff.f000.1cb8
PC = 0000.0000.0000.1d24
Decompressing in Memory Done
Size = 0000.0000.0007.01d0
ttya initialized
Using POST's System Configuration
Setting up memory
Starting CPU ID 1
Starting CPU ID 4
Starting CPU ID 5
Starting CPU ID 8
Starting CPU ID 9
Clock board TOD does not match TOD on any IO board.
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II
disk-board disk-board disk-board
Probing UPA Slot at 2,0   sbus fhc ac environment flashprom eeprom sbus-speed counter-timer
Probing UPA Slot at 3,0   sbus counter-timer
Probing UPA Slot at c,0   sbus fhc ac environment flashprom eeprom sbus-speed counter-timer
Probing UPA Slot at d,0   sbus counter-timer
Probing /sbus@2,0 at d,0  SUNW,soc
Probing /sbus@2,0 at 1,0  SUNW,socal sf ssd sf ssd
Probing /sbus@2,0 at 2,0  SUNW,socal sf ssd sf ssd
Probing /sbus@3,0 at 3,0  SUNW,hme SUNW,fas sd st
Probing /sbus@3,0 at 0,0  cgsix
Probing /sbus@c,0 at d,0  SUNW,soc
Probing /sbus@c,0 at 1,0  Nothing there
Probing /sbus@c,0 at 2,0  SUNW,socal sf ssd sf ssd
Probing /sbus@d,0 at 3,0  SUNW,hme SUNW,fas sd st
Probing /sbus@d,0 at 0,0  Nothing there
race

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0
2楼 [报告]
发表于 2005-03-08 08:05 |只看该作者

机器自检不通过, 连OBP也进不去(附自检信息)

是进入个POST诊断状态，把诊断相关的几个参数该回去就可以了
开机按STOP+N可以恢复NVRAM缺声状态。
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jndu

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3楼 [报告]
发表于 2005-03-08 11:51 |只看该作者

机器自检不通过, 连OBP也进不去(附自检信息)

楼主，这些post output你怎么抓下来的？
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kenny.ding

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4楼 [报告]
发表于 2005-03-08 12:36 |只看该作者

机器自检不通过, 连OBP也进不去(附自检信息)

[quote]原帖由 "jndu"]楼主，这些post output你怎么抓下来的？[/quote 发表：

我想,应该是通过串口吧,这没什么呀!
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jndu

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5楼 [报告]
发表于 2005-03-08 13:07 |只看该作者

机器自检不通过, 连OBP也进不去(附自检信息)

我没用过啊！
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天涯明月刀

招聘 : Linux运维
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0
6楼 [报告]
发表于 2005-03-08 14:01 |只看该作者

机器自检不通过, 连OBP也进不去(附自检信息)

STOP-N
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lyh003473

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7楼 [报告]
发表于 2005-03-08 15:05 |只看该作者

机器自检不通过, 连OBP也进不去(附自检信息)

用串口连接得按哪个键呀
实战分享：从技术角度谈机器学习入门| 【大话IT】RadonDB低门槛向MySQL集群下战书 | ChinaUnix打赏功能已上线！ | 新一代分布式关系型数据库RadonDB知多少？
jndu

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8楼 [报告]
发表于 2005-03-08 15:14 |只看该作者

机器自检不通过, 连OBP也进不去(附自检信息)

用stop + N 需要在NVRAM里设 diag-switch?=true 啊！
不设的话，没用
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3x3eyes

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9楼 [报告]
发表于 2005-03-08 16:49 |只看该作者

机器自检不通过, 连OBP也进不去(附自检信息)

大哥们,我想问
经常看见你们说post诊断,到底怎么做的啊
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rebellion

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10楼 [报告]
发表于 2005-03-09 01:31 |只看该作者

机器自检不通过, 连OBP也进不去(附自检信息)

谢谢各位大侠, 要想拷贝信息用TC连到串口, 或者直连线用tip命令就可以了
实战分享：从技术角度谈机器学习入门| 【大话IT】RadonDB低门槛向MySQL集群下战书 | ChinaUnix打赏功能已上线！ | 新一代分布式关系型数据库RadonDB知多少？
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