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Done
0>Interrupt Crosscall....Done
0>Init Memory..../
SC Alert: SC Request to send Break to host.
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****** POST Running ******
Done
0>PLL Reset....Done
0>Init Memory....Done
0>Test Memory....\
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = MB/P0/B1/D0 (Bank 2), Motherboard
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG = Pin 114 failed on MB/P0/B1/D0 (Bank 2), Motherboard
0>END_ERROR
0>
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = MB/P0/B1/D1 (Bank 2)
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG = Pin 2 failed on MB/P0/B1/D1 (Bank 2), Motherboard
0>END_ERROR
0>
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = MB/P0/B1/D1 (Bank 2), Motherboard
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG = Pin 4 failed on MB/P0/B1/D1 (Bank 2), Motherboard
0>END_ERROR
0>
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = MB/P0/B1/D1 (Bank 2), Motherboard
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG = ERROR: miscompare on mem test!
Address: 00000002.001b0000
Expected: 00000000.00000000
Observed: 000000ff.00ffdb00
0>END_ERROR
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0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = CPU0 Memory
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG =
*** Test Failed!! ***
0>END_ERROR
0>
0>ERROR: TEST = Data Bitwalk on Master
0>H/W under test = CPU0 Memory
0>Repair Instructions: Replace items in order listed by 'H/W under test' above.
0>MSG = No good memory available on master CPU 0, rolling over to new Master.
0>END_ERROR
Done
0>ERROR:
SC Alert: DISK @ HDD0 has been inserted.
0> POST toplevel status has the following failures:
0> MB/P0/B1/D0 (Bank 2), Motherboard
0> MB/P0/B1/D1 (Bank 2), Motherboard
0>END_ERROR
0>
0>ERROR: No good CPUs OR CPUs with good memory left. Calling debug menu
SC Alert: MB/P0/B1/D0 (Bank 2), Motherboard has been failed by POST
SC Alert: MB/P0/B1/D1 (Bank 2), Motherboard has been failed by POST
.
0> 0 Peek/Poke interface
0> 1 Dump CPU Regs
0> 2 Dump Valid L2$
0> 3 Dump Trap Table
0> 4 Dump Mem Controller Regs
0> 5 Dump Valid DMMU entries
0> 6 Dump IMMU entries
0> 7 Dump Mailbox
0> 8 Dump IO-Bridge regs
0> 9 Allow other CPUs to print
0> a Do soft reset
0> ? Help
0>
0>Selection: 帮我看看
[ 本帖最后由 气氛弥漫 于 2007-7-12 17:31 编辑 ] |
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