贴一个CPU的设计

cjaizss

About
The JAM CPU is a 32bit 5 stage pipelined RISC core with forwarding and hazard handling. Its basic design is derived from the DLX architecture (from the Patterson & Hennessy books). The JAM CPU core is implemented in VHDL and has been tested in an actual FPGA (the Xilinx Virtex I chip).

We have released the CPU core under the GNU Lesser General Public License (LGPL) in the hope that it will be useful for people studying VHDL or computer architecture.

Files
The full documentation ( .ps | .pdf )
The JAM CPU core!

Authors
The JAM CPU core is copyrighted (C) 2002 by
Anders Lindström
Johan E. Thelin
Michael Nordseth

cjaizss

以下是关于这款CPU的说明。

sep

好东西，狂顶。就是不知道这个cpu性能如何，能测试一下就好了。

wheel

收下拉...谢谢 了///

fangye1986

今天才发现这个好东东, 太棒了！

garyv

移植个super pi，跑跑看性能怎么样

fangye1986

这设计仅能胜任教学用途, 这也是作者的初衷

5级顺序流水线, 单发射, 不支持浮点运算... 还有人去指望功能性能啊

keyjing

god

bluesea666

学习了.

jefong

很好，学习。